Design of a Robust Logic Gate Using Magnetic Tunnel Junction

Title: Design of a Robust Logic Gate Using Magnetic Tunnel Junction
Author: Kanika Monga, Nitin Chaturvedi, S. Gurunarayanan
Affiliation: Birla Institute of Technology and Science, Pilani, India


Abstract: In the era of big data, limited communication bandwidth poses a great challenge for conventional Von-Neumann architecture. Moreover, significant data movement between memory and processor to handle ever-growing data set further degrade the system performance. To address this issue the most efficient way is to perform computation within the memory. This promising solution of integrating logic within the memory avoids expensive data transfers between memory and processor thereby resulting in higher performance and energy efficiency. Therefore, in this paper emerging non-volatile memory such as Magnetic Random Access Memory (MRAM) is explored as one of the most promising candidates to compute within the memory. It offers several additional advantages such as zero standby leakage power consumption and instant-on capability. This work presents the structure of Computational Random-Access Memory (CRAM) and design of universal logic gates such as NAND and NOR. Next, to increase the reliability of these gates a novel technique is proposed which significantly reducing the functional error probability.

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